ISL5827INZ【PDF 4/13 页】IC DAC DUAL 12BIT 3.3V 48-LQFP

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theoretically improving the even order harmonic rejection,

but likely reducing the signal swing available due to the

output voltage compliance range limitations.

Propagation Delay

The converter requires two clock rising edges for data to be

represented at the output. Each rising edge of the clock

captures the present data word and outputs the previous

data. The propagation delay is therefore 1/CLK, plus <2ns of

processing. See Figure 15.

Test Service

Intersil offers customer-specific testing of converters with a

service called Testdrive. To submit a request, fill out the

Testdrive form at www.intersil.com/testdrive. Or, send a

request to the technical support center.

RDIFF

ISL5827

RLOAD

FIGURE 13. OUTPUT LOADING FOR DATASHEET

MEASUREMENTS

OUTA

OUTB

VOUT = (2 x OUTA x REQ)V

LOAD SEEN BY THE TRANSFORMER

RLOAD REPRESENTS THE

1:1

REQ = 0.5 x (RLOAD//RDIFF)

AT EACH OUTPUT

FIGURE 14. ALTERNATIVE OUTPUT LOADING

ISL5827

OUTA

OUTB

VOUT = (2 x OUTA x REQ)V

REQ = 0.5 x (RLOAD//RDIFF//RA), WHERE RA = RB

AT EACH OUTPUT

RLOAD

RDIFF

LOAD SEEN BY THE TRANSFORMER

RLOAD REPRESENTS THE

Timing Diagram

FIGURE 15. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM

CLK

IOUT

50%

tPW1

tPW2

tSU

tHLD

tSU

tPD

tHLD

D11-D0

OUTPUT = W0

OUTPUT = W1

tPD

OUTPUT = W-1

ISL5827

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